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Freescale Semiconductor Technical Data
Document Number: MC33298 Rev. 5.0, 10/2006
Eight Output Switch with Serial Peripheral Interface I/O
The 33298 is a smart eight-output low-side power switch. It is a versatile device incorporating an 8-bit serial-in shift register to control an 8-bit parallel output latch providing control of eight independent "ON/OFF" output switches. Applications include the control of solenoids, relays, lamps, small DC-motors, and other moderate current loads (1.0 - 3.0 A). The 33298 interfaces directly with a microcontroller to control various inductive or incandescent loads. Input control is fast. Data rates are guaranteed to 2.0 MHz but the device is capable of rates to 8.5 MHz @ 25C. Each output uses high-efficiency MOSFET power transistors configured with open drains. Each low "ON" resistance output (0.4 RDS(ON) @ 25C) is capable of sinking up to 3.0 A of transient current. On a continuous basis, each output can simultaneously (with all outputs "ON") handle 0.5 A of current when the device is soldered onto a typical PC board. Higher output currents are dependent on the number of outputs simultaneously "ON". The circuit's innovative monitoring and protection features include very low standby current. Features
33298
LOW-SIDE SWITCH
DW SUFFIX EG SUFFIX (PB-FREE) 98ASB42344B 24 SOICW
ORDERING INFORMATION
Device MC33298DW/R2 -40C to 125C 24 SOIC Temperature Range (TA) Package
* Designed to Operate Over Wide Supply Voltages of 5.5 to 26.5 V MCZ33298EG/R2 * Interfaces to Microprocessor Using 8-Bit SPI I/O Protocol up to 3.0 MHz * 1.0 A Peak Current Outputs with Maximum RDS(on) of 1.6 at TJ - 150C * Outputs Current Limited to Accommodate In-rush Currents Associated with Switching Incandescent Loads * Output Voltages Clamped to 53 V During Inductive Switching * Maximum Sleep Current (IPWR) of 25 A * Maximum of 4.0 mA IDD During Operation * Pb-Free Packaging Designated by Suffix Code EG
VDD
V PWR
33298
VPWR SFPD VDD CS MCU SCLK SI SO RESET OP 0 OP 1 OP 2 OP 3 OP 4 OP 5 OP 6 OP 7 GND
Figure 1. 33298 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products.
(c) Freescale Semiconductor, Inc., 2006. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VPWR
21
OUTPUT 0 Over Voltage OVD VDD RB SFPD SFL CS SCLK SI SO CSI CSBI Voltage Regulator GE OT SF OF 24 Bias
53 V
VDD 16 SFPD 15 RST 22
+
10 A 25 A +
Gate Control
OUTPUT 1 to 7 To Gates 1 to 7
2 11 - 14
CS 10 SCLK 3 SI 4 SO 9
10 A Fault Timers 10 A + 10 A Serial D/O Line Driver
SPI Interface Logic
Open Load Detect
lLimit
+ -
23
Short Circuit Detect
RS
Over Temperature Detect From Detectors 1 to 7
GND 5-8 17-20
Figure 2. 33298 Simplified Block Diagram Table 1. Fault Operation
SERIAL OUTPUT (SO) PIN REPORTS Overvoltage Overtemperature Overcurrent Output ON, Open Load Fault Overvoltage condition reported Fault reported by Serial Output (SO) pin SO pin reports short to battery/supply or over current condition Not reported
Output OFF, Open Load Fault SO pin reports output OFF open load condition DEVICE SHUTDOWNS Overvoltage Overtemperature Overcurrent Total device shutdown at VPWR = 28 to 36 V. All outputs are latched off while the SPI register is reset (cleared). Outputs can be turned back on with a new SPI command after VPWR has decayed below 26.5 V. Only the output experiencing an overtemperature condition turns off. Only the output experiencing an over current shuts down at 1.0 to 3.0 A after a 70 to 250 s delay, with SFPD pin grounded. All other outputs will continue to operate in a current limit mode, with no shutdown, if the SFPD pin is at 5.0 V (so long as the individual outputs are not experiencing thermal limit conditions).
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Analog Integrated Circuit Device Data Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
OP7 OP8 SCLK SI GND GND GND GND SO CS OP5 OP4
1 2 3 4 5 6 7
24 23 22 21 20 19 18
OP0 OP1 RST VPWR GND GND GND GND VDD SFPD OP2 OP3
8
9
17
16
10 11 12
15 14 13
Figure 3. 33298 Pin Connections Table 2. 33298 Pin Function Description
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Pin Name OP7 OP6 SCLK SI GND GND GND GND SO CS OP5 OP4 OP3 OP2 SFPD VDD GND GND GND GND VPWR RST Formal Name Output 7 Output 6 System Clock Serial Input Ground Ground Ground Ground Serial Output Chip Select Output 5 Output 4 Output 3 Output 2 Short Fault Protect Disable Logic Supply Ground Ground Ground Ground Power RESET Definition This pin provides connection to drain of output MOSFET number seven. This pin provides connection to drain of output MOSFET number six. This pin clocks the internal Shift registers of the 33298. This pin is for the input of serial instruction data. SI information is read on the falling edge of SCLK. This pin provides connection to IC Power Ground and functions as part of heat sinking path. This pin provides connection to IC Power Ground and functions as part of heat sinking path. This pin provides connection to IC Power Ground and functions as part of heat sinking path. This pin provides connection to IC Power Ground and functions as part of heat sinking path. This pin is the tri-stateable output from the Shift register. Whenever this pin is in a logic low state, data can be transferred from the MCU to the 33298 through the SI pin and from the 33298 to the MCU through the SO pin. This pin provides connection to drain of output MOSFET number five. This pin provides connection to drain of output MOSFET number four. This pin provides connection to drain of output MOSFET number three. This pin provides connection to drain of output MOSFET number two. This pin is used to prevent the outputs from latching-OFF because of an over current condition. Logic Supply. This pin provides connection to IC Power Ground and functions as part of heat sinking path. This pin provides connection to IC Power Ground and functions as part of heat sinking path. This pin provides connection to IC Power Ground and functions as part of heat sinking path. This pin provides connection to IC Power Ground and functions as part of heat sinking path. Output MOSFET Gate Drive Supply. This pin is active low. It is used to clear the SPI Shift register, thereby setting all output switches OFF.
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PIN CONNECTIONS
Table 2. 33298 Pin Function Description (continued)
Pin Number 23 24 Pin Name OP1 OP0 Formal Name Output 1 Output 0 Definition This pin provides connection to drain of output MOSFET number one. This pin provides connection to drain of output MOSFET number zero.
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Rating Power Supply Voltage Normal Operation (Steady-State) Transient Conditions (1) Logic Supply Voltage (2) Input pin Voltage (3) Output Clamp Voltage (4) 2.0 mA IOUT 0.5 A Output Self-Limit Current Continuous Per Output Current (5) ESD Voltage
(6)
Symbol
Value
Unit V
VPWR(SS) VPWR(PK) VDD VIN VOUT(OFF)
- 1.5 to 26.5 - 13 to 60 - 0.3 to 7.0 - 0.3 to 7.0 50 to 75 V V V
IOUT(LIM) IOUT(CONT) VESD1 VESD2 ECLAMP
3.0 to 6.0 1.0 2000 200
A A V
Human Body Model (7) Machine Model (7) Output Clamp Energy (8) Repetitive: TJ = 25C TJ = 124C Non-Repetitive: TJ = 25C TJ = 124C Recommended Frequency of SPI Operation (9) Storage Temperature Peak Package Reflow Temperature During Reflow (10), (11) Notes 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11.
100 30 2.0 0.5 fSPI TSTG TPPRT 2.0 - 55 to 150 Note 11.
mJ mJ J J MHz
C
C
Transient capability with external 100 resistor in series with VP pin and supply. Exceeding these limits may cause a malfunction or permanent damage to the device. Exceeding the limits on SCLK, SI, CS, SFPD, or RST pins may cause permanent damage to the device. With output OFF. Continuous output current rating so long as maximum junction temperature is not exceeded. Operation at 125C ambient temperature will require maximum output current computation using package RJA. ESD data available upon request. ESD1 testing is performed in accordance with the Human Body Model (CZap = 200 pF, RZap = 1500 ), ESD2 testing is performed in accordance with the Machine Model (CZap = 200pF, RZap = 0 ). Maximum output clamp energy capability at 150C junction temperature using a single non-repetitive pulse method. Guaranteed and production tested for 2.0 MHz SPI operation, but demonstrated to operate to 8.5 MHz at 25C. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standerd J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), > Go to www.freescale.com > Search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx)] > Locate your Part Number and in the Details column, select "View" > Select "Environmental and Compliance Information"
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
Table 4. Maximum Ratings (continued) All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Rating Operating Case Temperature Operating Junction Temperature Power Dissipation (TA = 25C) Case 738 Package All Outputs ON (15) Single Output ON (15) Case 751E Package All Outputs ON (14) Single Output ON (15) 34 40 31 37
(12)
Symbol TC TJ PD RJA
Value - 40 to 125 - 40 to 150 3.0
Unit
C C
W
(13)
Thermal Resistance (Junction-to-Ambient)
C/W
Notes 12. See Figure 20 for Thermal model. 13. Soldering temperature limit is for 10 seconds maximum duration; not designed for immersion soldering; exceeding these limits may cause malfunction or permanent damage to the device.Contact Freescale Semiconductor Sales Office for device immersion soldering time/temperature limits. 14. Thermal resistance from Junction-to-Ambient with all outputs ON and dissipating equal power. 15. Thermal resistance from Junction -to-Ambient with a single output ON.
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics Characteristics noted under conditions 4.5 V VDD 5.5 V, 9.0 V VPWR 16 V, -40C TA 125C, unless otherwise noted. Typical values noted reflect the approximate value with VBat = 13 V, TA = 25C.
Characteristic POWER INPUT Supply Voltage Range Quasi-Functional (16) Fully Operational Supply Current (All Outputs ON, IOUT = 0.5 A) Sleep State Supply Current (VDD = 0.5 V) Sleep State Output Leakage Current (per Output, VDD = 0.5V) Over Voltage Shutdown Over Voltage Shutdown Hysteresis Logic Supply Voltage Logic Supply Current (with any combination of Outputs ON) Logic Supply Under Voltage Lockout Threshold POWER OUTPUT Drain-to-Source ON Resistance (IOUT = 0.5 A, TJ = 25C) VPWR = 5.5 V VPWR = 9.0 V VPWR = 13 V Drain-to-Source ON Resistance (IOUT = 0.5 A, TJ = 150C) VPWR = 5.5 V VPWR = 9.0 V VPWR = 13 V Output Self-Limiting Current Outputs Programmed ON, VOUT = 0.6 VDD Output Fault Detect Threshold (19) Output Programmed OFF Output OFF Open Load Detect Current
(20) (18) (17)
Symbol
Min
Typ
Max
Unit
V VPWR(QF) VPWR(FO) VPWR(ON) IPWR(SS) IOUT(SS) VOV VOV(HYS) VDD IDD VDD(UVLO) 5.5 9.0 -- -- -- 28 0.2 4.5 -- 2.0 -- -- 1.0 1.0 -- -- -- -- -- -- 9.0 26.5 2.0 50 50 36 1.5 5.5 4.0 4.5 V A A V V V mA V
RDS(ON)
-- -- -- -- 0.4 0.35 10 0.5 0.45 -- -- -- -- 7.5 0.65 1.8 0.9 0.8 A 3.0 4.0 6.0 VDD 0.6 0.7 0.8 A 30 50 100 V 50 60 0 75 50 A
RDS(ON)
IOUT(LIM)
VOUTth(F) IOCO
Output Programmed OFF, VOUT = 0.6 VDD Output Clamp Voltage 2.0 mA < IOUT < 200 mA Output Leakage Current (VDD < 2.0 V)
(21)
VOK
IOUT(LKG)
-50
Notes 16. SPI inputs and outputs operational; Fault status reporting may not be fully operational within this voltage range. 17. Value reflects normal operation (no faults) with all outputs ON. Each ON output contributes approximately 20 A to IPWR. Each output experiencing a soft short condition contributes approximately 0.5 mA to IPWR. A soft short is defined as any load current causing the output source current to self-limit. A hard output short is a very low impedance short to supply. 18. For VDD less than the Under Voltage Lockout Threshold voltage, all data registers are reset and all outputs are disabled. 19. 20. 21. Output Fault Detect Threshold with outputs programmed OFF. Output fault detect thresholds are the same for output opens and shorts. Output OFF Open Load Detect Current is the current required to flow through the load for the purpose of detecting the existence of an open load condition when the specific output is commanded to be OFF. Output leakage current measured with the output OFF and at 16 V.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 6. Static Electrical Characteristics (continued) Characteristics noted under conditions 4.5 V VDD 5.5 V, 9.0 V VPWR 16 V, -40C TA 125C, unless otherwise noted. Typical values noted reflect the approximate value with VPWR = 13 V, TA = 25C.
Characteristic Over Temperature Shutdown (Outputs OFF) Over Temperature Shutdown Hysteresis DIGITAL INTERFACE Input Logic High Voltage (23) Input Logic Low Voltage (24) Input Logic Voltage Hysteresis (25) Input Logic Current (26) RST Pull-Up Current (RST = 0.7 VDD) SFPD Pull-Down Current (SFPD = 0.2 VDD) SO High State Output Voltage (IOH = 1.0 mA) SO Low State Output Voltage (IOL = -1.6 mA) SO Tri-State Leakage Current (CS = 0.7 VDD, 0 V < VSO < VDD) Input Capacitance (0 V < VDD < 5.5 V) (27) SO Tri-State Capacitance (0 V < VDD < 5.5 V) (28) Notes 22. 23. 24. 25. 26. 27. 28. VIH VIL VI(HYS) IIN IRST ISFPD VSOH VSOL ISOT CIN CSOT 0.7 0 50 -10 10 10 -- -- 100 0 22 22 1.0 0.2 500 10 50 50 -- 0.4 10 12 20 VDD VDD mV A A A V V A pF pF
(22) (22)
Symbol TLIM TLIM(HYS)
Min 155 --
Typ 170 10
Max 185 20
Unit
C C
VDD -1.0 V VDD -0.6 V -- -10 -- -- 0.2 0 -- --
This parameter is guaranteed by design, but it is not production tested. Upper and lower logic threshold voltage levels apply to SI, CS, SCLK, RST, and SFPD inputs. Lower logic threshold voltage range applies to SI, CS, SCLK, Reset, and SFPD input signals. Only the SFPD and Reset inputs have hysteresis. This parameter is guaranteed by design, but it is not production tested. Input current of SCLK, SI and CS logic control inputs. Input capacitance of SI, CS, SCLK, RST, and SFPD for 0 V < VDD < 5.5 V. This parameter is guaranteed by design, but it is not production tested. Tri-state capacitance of SO for 0 V < VDD < 5.5 V. This parameter is guaranteed by design, but it is not production tested.
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
.
Table 7. Dynamic Electrical Characteristics Characteristics noted under conditions 4.5 V VDD 5.5 V, 9.0 V VPWR 16 V, -40C TA 125C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic POWER OUTPUT TIMING Output Rise Time (VPWR = 13 V, RL = 26 ) (29) Output Fall Time (VPWR = 13 V, RL = 26 )
(29) (30) (31)
Symbol
Min
Typ
Max
Unit
tR tF tDLY(ON) tDLY(OFF) tDLY(SF)
0.4 0.4 1.0 1.0
1.5 2.5 5.0 5.0
20 20 15 15
s s s s s
Output Turn ON Delay Time (VPWR = 13 V, RL = 26 )
Output Turn-OFF Delay Time (VPWR = 13 V, RL = 26 ) Output Short Fault Disable Report Delay SFPD = 0.2 x VDD Output OFF Fault Report Delay (33) SFPD = 0.2 x VDD DIGITAL INTERFACE TIMING SCLK Clock Period (34) SCLK Clock High Time SCLK Clock Low Time Required Low State Duration for Reset (VIL < 0.2 VDD)
(32)
25 tDLY(OFF) 25
50
100 s
50
100
tpSCLK twSCLKH twSCLKL
(35)
500 175 175 250 250 250 125 125 -- -- -- -- -- --
-- -- -- 50 50 50 25 25 25 25 -- -- -- --
-- -- -- -- -- -- -- -- 75 75 200 200 200 200
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tw(RST) tLEAD tLAG tSISU tSI(HOLD) trSO tfSO
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) Falling Edge of SCLK to Rising Edge of CS (Required for Setup Time) SI to Falling Edge of SCLK (Required for Setup Time) Falling Edge of SCLK to SI (Required for Hold Time) SO Rise Time (CL = 200 pF) SO Fall Time (CL = 200 pF) SI, CS, SCLK, Incoming Signal Rise Time SI, CS, SCLK, Incoming Signal Fall Time
(36)
trSI tfSI
(37) (38)
(36)
Time from Falling Edge of CS to SO Low Impedance Time from Rising Edge of CS to SO High Impedance
tSO(EN) tSO(DIS)
Notes 29. Output Rise and Fall time respectively measured across a 26 resistive load at 10 to 90 percent, and 90 to 10 percent voltage points. 30. Output Turn ON Delay time measured from 50 percent rising edge of CS to 90 percent of Output OFF voltage (VPWR) with RL = 26 resistive load. 31. Output Turn OFF Delay time measured from 50 percent rising edge of CS to 10 percent of Output OFF voltage (VPWR) with RL = 26 resistive load. 32. Output Short Fault Delay time measured from rising edge of CS to IOUT -= 2.0 A point with output ON, VOUT = 5.0 V, and SFPD = 0.2 x VDD. See Figures 8 and 10. 33. 34. 35. 36. 37. 38. Output OFF Fault Report Delay measured from 50 percent rising edge of CS to rising edge of output. See Figure 9. Clock period include 75 ns rise plus 75 ns fall transition in addition to clock high and low time. RST Low duration measured with outputs enabled and going to OFF or disabled condition. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. Time required for output status data to be available for use at the SO pin. Time required for output status data to be terminated at the SO pin.
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
Table 7. Dynamic Electrical Characteristics Characteristics noted under conditions 4.5 V VDD 5.5 V, 9.0 V VPWR 16 V, -40C TA 125C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic Time from Rising Edge of SCLK to SO Data Valid (39) 0.2 VDD < SO > 0.8 VDD, CL = 200 pF Notes 39. Time required to obtain valid data out from SO following the rise of SCLK. See Figure 5. Symbol tVALID -- 50 125 Min Typ Max Unit ns
.
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS
TIMING DIAGRAMS
VIH
RST
0.2 VDD tw(RST) VIL VIH 0.2 VDD tLEAD 0.7 VDD tw(SCLKH) tR tLAG VIH 0.2 VDD tw(SCLKL) tSI(su) 0.7 VDD tSI(hold) Don't Care tF VIH Valid 0.2 VDD Valid Don't Care VIL VIL VIL
CS
SCLK
SI
Don't Care
Figure 4. Input Timing Switch Characteristics
ELECTRICAL PERFORMANCE CURVES
VDD = 5.0 V
VDD = 5.0 V
VPull-Up = 2.5 V
RL = 1.0 k
33298 33298
SCLK Under Test SO CL = 200 pF
CS
Under Test
SO CL = 20 pF
L

CL represents the total capacitance of the test fixture and probe.
Figure 5. Valid Data Delay Time and Valid Time Test Circuit
Figure 6. Enable and Disable Time Test Circuit
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ELECTRICAL CHARACTERISTICS ELECTRICAL PERFORMANCE CURVES
tR (SI) < 10 ns 0.7 VDD 50%
tF (SI) < 10 ns
5.0 V
0.2 VDD
VDD = 5.0 V
VPWR = 14 V
SCLK
tDLY(LH)
0 V0H
RL = 26
0.7 VDD
33298
V0L V0H
CS Under Test CL Output
SO
(Low-to-High)
0.2 VDD
SO
(High-to-Low)
tVALID
0.7 VDD
tR (SO) tF (SO)
0.2 VDD
tDLY(HL)
V0L
SO (Low-to-High) is for an output with internal conditions such that the low-to-high transition of CS causes the SO output to switch from high to low.
CL represents the total capacitance of the test fixture and probe.
Figure 9. Switching Time Test Circuit
Figure 7. Valid Data Delay Time and Valid Time Waveforms
VDD = 5.0 V VPWR = 11 V
CS
0.2 VDD
tR(SI) < 10 ns
tF(SI) < 10 ns 0.7 VDD 5.0 V 0
90% 10% tSO(EN) 90%
33298
CS Under Test
L = 2.0 ( ) Output CL = 20 pF
SO
(High-to-Low)
tSO(DIS) VTri-State 10%
tSO(dis)
tSO(EN) 90%
tSO(DIS)
V0H
SO
(Low-to-High)
10%
VTri-State
CL .
1. SO (high-to-low) waveform is for SO output with internal conditions such that SO output is low except when an output is disabled as a result of detecting a circuit fault with CS in a High Logic state, e.g. open load. 2. SO (low-to-high) waveform is for SO output with internal conditions such that SO output is high except when an output is disabled as a result of detecting a circuit fault with CS in a High Logic state, e.g. shortened load.
Figure 10. Output Fault Unlatch Disable Delay Test Circuit
Figure 8. Enable and Disable Time Waveforms
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS ELECTRICAL PERFORMANCE CURVES
tR(SI)
< 10 ns 90% 50%
tF(SI)
tR(SI) < 10 ns 5.0 V < 10 ns
tF(SI) < 10 ns 90% 10% 5.0 V 0 VOFF = 11 V 50% tDLY(OFF) VON = 5.0 V IO(CL) 0
CS
10% 0 14 V
50%
CS
tDLY(OFF)
Output Voltage
Output Voltage Waveform
Waveform 1
50%
VOL 14 V
Output Voltage
Waveform 2
tDLY(ON)
50% VOL
Output Current Waveform
50%
and are turn-on and turn-off propagation delay times. 2. Turn-off is an output programmed from an ON to an OFF state. 3. Turn-on is an output programmed from and OFF to an ON state.
1. tDLY(ON)
tDLY(OFF)
1. tPDLY(OFF) is the output fault unlatch disable propagation delay time required to correctly report an output fault after CS rises. It represents an output commanded ON while having an existing output short (over current) to supply. 2. The SFPD pin < 0.2 V
Figure 11. Turn-On/Off Waveforms
Figure 12. Output Fault Unlatch Disable Delay Waveforms
33298
Analog Integrated Circuit Device Data Freescale Semiconductor
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FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33298 was conceived, specified, designed, and developed for automotive applications. It is an eight output low side power switch having 8-bit serial control. The 33298 incorporates SMARTMOSTM technology having effective 1.5 CMOS logic, bipolar/MOS analog circuitry, and independent state of the art double diffused MOS (DMOS) power output transistors. Many benefits are realized as a direct result of using this mixed technology. A simplified block diagram delineates 33298 in Figure 1. Where bipolar devices require considerable control current for their operation, structured MOS devices, since they are voltage controlled, require only transient gate charging current affording a significant decrease in power consumption. The CMOS capability of the SMARTMOSTM process allows significant amounts of logic to be economically incorporated into the monolithic design. Additionally, the bipolar/MOS analog circuits embedded within the updrain power DMOS output transistors monitor and provide fast, independent protection control functions for each individual output. All outputs have internal 45 V at 0.5 A independent output voltage clamps to provide fast inductive turn-off and transient protection. The 33298 uses high efficiency updrain power DMOS output transistors exhibiting very low room temperature drain-to-source ON resistance values (RDS(on) 1.0 at 13 V VPWR) and dense CMOS control logic. Operational bias currents of less than 2.0 mA (1.0 mA typical) with any combination of outputs ON are the result of using this mixed technology and would not be possible with bipolar structures. To accomplish a comparable functional feature set using a bipolar structure approach would result in a device requiring hundreds of milliamperes of internal bias and control current. This would represent a very large amount of power to be consumed by the device itself and not available for load use. During operation, the 33298 functions as an eight output serial switch serving as a microcontroller (MCU) bus expander and buffer with fault management and fault reporting features. In doing so, the device directly relieves the MCU of the fault management functions. The 33298 directly relieves the MCU of the fault management functions. The 33298 directly interfaces to an MCU, operating at system clock serial frequencies in excess of 3.0 MHz. It uses a Synchronous Peripheral Interface (SPI) for control and diagnostic readout. Figure 11 illustrates the basic SPI configuration between an MCU and one 33298.
MC68HCXX Microcontroller MOSI
Shift Register
33298 SI SO
Shift Register
MISO
Receive Buffer Parallel Ports
SCLK
To Logic
RST CS
Figure 13. SPI Interface with Microcontroller The circuit can also be used in a variety of other applications in the computer, telecommunications, and industrial fields. It is parametrically specified over an input battery /supply range of 9.0 to 16 V but is designed to operate over a considerably wider range of 5.5 to 26.5 V. The design incorporates the use of Logic Level MOSFETs as output devices. These MOSFETs are sufficiently turned ON with a gate voltage of less than 5.0 V thus eliminating the need for an internal charge pump. Each output is identically sized and independent in operation. The efficiency of each output transistor, at room temperature provides as little as 9.0 V supply (VPWR), the maximum RDS(on) of an output All inputs are compatible with 5.0 V CMOS logic levels, incorporating negative or inverted logic. Whenever an input is programmed to a logic low state (<1.0 V) the corresponding low side switched output being controlled will be active low and turned ON. Conversely, whenever an input is programmed to a logic high state (>3.0 V), the output being controlled will be high and turned OFF.
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION INTRODUCTION
SCLK Parallel Port
CS MC68XX Microcontroller SPI MISO SO IRQ
SCLK SI
CS SO
SCLK SI
CS SO
SCLK SI
CS SO
SCLK SI
33298
8 Outputs
33298
8 Outputs
33298
8 Outputs
33298
8 Outputs
MOSI
Figure 14. 33298 SPI System Daisy Chain One main advantage of the 33298 is the serial port. When supplies the system clock signal (top MCU designated the coupled to an MCU, it receives ON/OFF commands from the master); the lower MCU being the slave. It is possible to have MCU and in return transmits the drain status of the device's a system with more than one master; however, not at the output switches. Many devices can be daisy-chained same time. Only when the master is not communicating can together, forming a larger system, illustrated in Figure 12. a slave assume the mastership and communicate. MCU master control is switched through the use of the slave select Note In this example, only one dedicated MCU parallel (SS) pin of the MCUs. A master will become a slave when it port (aside from the required SPI) is required for chip select detects a logic low state on its SS pin. to control 32 possible loads. These basic examples make the 33298 very attractive for Multiple 33298 devices can also be controlled in a parallel applications where a large number of loads require efficient input fashion using SPI, illustrated in Figure 13. This figure control. To this end, the popular Synchronous Serial shows a possible 24 loads being controlled by only three Peripheral Interface (SPI) protocol is incorporated to dedicated parallel MCU ports used for chip select. communicate efficiently with the MCU.
33298 MOSI SCLK MC68XX Microcontroller SPI SI SCLK CS 8 Outputs
SPI SYSTEM ATTRIBUTES
The SPI system is flexible enough to communicate directly with numerous standard peripherals and MCUs available from Freescale Semiconductor and other semiconductor manufacturers. SPI reduces the number of pins necessary for input/output (I/O) on the 33298. It also offers an easy means of expanding the I/O function using few MCU pins. The SPI system of communication consists of the MCU transmitting, in return it receives one data-bit of information per system clock cycle. Data-bits of information are simultaneously transmitted by one pin, Microcontroller Out Serial In (MOSI), and received by another pin, Microcontroller In Serial Out (MISO), of the MCU. Some features of SPI are: * Full duplex, three-wire synchronous data transfer * Each microcontroller can be a master or a slave * Provides write collision flag protection * Provides end of message interrupt flag * Four I/Os associated with SPI (MOSI, MISO, SCLK, SS) Drawbacks to SPI are: * An MCU is required for efficient operational control * In contrast to parallel input control it Is slower at performing pulse width modulating (PWM) functions.
33298 SI Parallel Ports A B C SCLK CS 8 Outputs
33298 SI SCLK CS 8 Outputs
Figure 15. Parallel Input SPI Control Figure 14 illustrates a basic method of controlling multiple 33298 devices using two MCUs. A system can have only one master MCU at any given instant of time and one or more slave MCUs. Master control of the system must pass from one MCU to the other in an orderly manner. The master MCU
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FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL PIN DESCRIPTION
MC68XX Microcontroller SPI (Master) A0 B0 B1 Parallel A1 Ports A2
8-Bit
33298 CS SCLK
8-Bit
8 Outputs
SO SCLK MISO MOSI 33298 SS MC68XX Microcontroller SPI
(Alternate Master)
SI
VDD
CS SCLK
8-Bit
8 Outputs
SO SI
B0 Parallel A0 B1 Ports A1 A2 SCLK
8-Bit
33298 CS SCLK
8-Bit
8 Outputs
MISO
SO SI
VDD
SS
MOSI
Figure 16. Multiple MCU SPI Control
CHIP SELECT (CS)
The 33298 receives its MCU communication through the CS pin. Whenever this pin is in a logic low state, data can be transferred from the MCU to the 33298 by way of the SI pin and from the 33298 to the MCU through the SO pin. Clockedin data from the MCU is transferred from the 33298 Shift register and latched into the power outputs on the rising edge of the CS signal. On the falling edge of the CS signal, drain status information is transferred from the power outputs then loaded into the Shift register of the device. The CS pin also controls the output driver of the serial output (SO) pin. Whenever the CS pin goes to a logic low state, the SO pin output driver is enabled allowing information to be transferred from the 33298 to the MCU. To avoid data corruption or the generation of spurious data, it is essential the high-to-low transition of the CS signal occur only when SCLK is in a logic low state.
any transition. For this reason, it is recommended, though not absolutely necessary, the SCLK pin be kept in a low logic state as long as the device is not accessed (CS in logic high state). When CS is in a logic high state, signals at the SCLK and SI pins are ignored and SO is tri-stated (high impedance). See the Data Transfer Timing diagram in Figure 16.
SERIAL INPUT (SI)
This pin is for the input of serial instruction (SI) data. SI is read on the falling edge of SCLK. A logic high state present on this pin when the SCLK signal rises will program a specific output OFF. In turn, the pin turns OFF the specific output on the rising edge of the CS signal. Conversely, a logic low state present on the SI pin will program the output ON, In turn, the pin turns ON the specific output on the rising edge of the CS signal. To program the eight outputs of the 33298 ON or OFF, an 8-bit serial stream of data is required to be synchronously entered into the SI pin starting with Output 7, followed by Output 6, Output 5, and so on, to Output 0. Referring to Figure 15, the DO bit is the most significant bit (MSB) corresponding to Output 7. For each rise of the SCLK signal, with CS held in a logic low state, a data-bit instruction (ON or OFF) is synchronously loaded into the Shift register per the data-bit SI state. The Shift register is full after eight bits of information have been entered. To preserve data integrity,
SYSTEM CLOCK (SCLK)
The system clock (SCLK) pin clocks the internal shift registers of the 33298. The serial input (SI) pin accepts data into the Input Shift register on the falling edge of the SCLK signal while the serial output (SO) pin shifts data information out of the SO line driver on the rising edge of the SCLK signal. False clocking of the Shift register must be avoided to guarantee validity of data. It is essential the SCLK pin be in a logic low state whenever the chip select bar (CS) pin makes
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION INTRODUCTION
care should be taken to not transition SI as SCLK transitions from a low-to-high logic state.
VDD
RDLY
+ 20 A Reset
SERIAL OUTPUT (SO)
The serial output (SO) pin is the tri-stateable output from the Shift register. The SO pin remains in a high impedance state until the CS pin goes to a logic low state. The SO data reports the drain status, either high or low relative to the previous command word. The SO pin changes state on the rising edge of SCLK and reads out on the falling edge of SCLK. When an output is OFF and not faulted, the corresponding SO data-bit is a high state. When an output is ON, and there is no fault, the corresponding data-bit on the SO pin will be a low logic state. The SI/SO shifting of data follows a first-in-first-out (FIFO) protocol with both input and output words transferring the MSB first. Referring to Figure 16, the DO bit is the MSB corresponding to Output 7 relative to the previous command word. The SO pin is not affected by the status of the Reset pin.
Reset MCU
CDLY
33298
Figure 17. Power ON Reset
SHORT FAULT PROTECT DISABLE (SFPD)
The Short Fault Protect Disable (SFPD) pin is used to prevent the outputs from latching-off due to an over current condition. This feature provides control of incandescent lamp loads where in-rush currents exceed the device's analog current limits. Essentially the SFPD pin determines whether the 33298 output(s) will instantly shutdown upon sensing an output short or remain ON in a current limiting mode of operation until the output short is removed or thermal shutdown is reached. If the SFPD pin is tied to VDD = 5.0 V the 33298 output(s) will remain ON in a current limited mode of operation upon encountering a load short to supply or over current condition. When the SFPD pin is grounded, a short circuit will immediately shut down only the output affected. Other outputs not having a fault condition will operate normally. The short circuit operation is addressed in more detail later.
RESET (RST)
The 33298 reset (RST) pin is active low. It is used to clear the SPI Shift register. In doing so, all output switches are set at OFF. The device situated in the same system with an MCU, the MCU retains the Reset pin of the device in a logic low state. Retention ensures all outputs to be OFF until both the VDD and VPWR pin voltages are adequate for predictable operation. Retention of the device Reset pin takes place only upon initial system power up. After the 33298 is reset, the MCU is ready to assert system control with all output switches initially OFF. If the VPWR pin of the 33298 experiences a low voltage, following normal operation, the MCU should pull the Reset pin low to shutdown the outputs and clear the input data register. The Reset pin is active low and has an internal pulldown incorporated, insuring operational predictability should the external pull-down of the MCU open circuit. The internal pull-down is only 25 A, affording safe and easy interfacing to the MCU. The Reset pin of the 33298 should be pulled to a logic low state for a duration of at least 250 ns, ensuring reliable a reset. A simple power ON reset delay of the system can be programmed through the use of an RC network comprised of a shunt capacitor from the Reset pin to Ground and a resistor to VDD, illustrated in Figure 15. Care should be exercised ensuring proper discharge of the capacitor. Careful attention eliminates adverse delay of the Reset and damage of the MCU if it pulls the Reset line low, thereby accomplishing initialization for turn ON delay. It may be easier to incorporate delay into the software program and use a parallel port pin of the MCU to control the 33298 Reset pin.
POWER CONSUMPTION
The 33298 has extremely low power consumption in both the operating and standby modes. In the standby, or Sleep mode, with VDD 2.0 V, the current consumed by the VPWR pin is less than 25 A. In the operating mode, the current drawn by the VDD pin is less than 4.0 mA (1.0 mA typical) while the current drawn at the VPWR pin is 2.0 mA maximum (1.0 mA typical). During normal operation, turning outputs ON increases IPWR by only 20 A per output. Each output experiencing a soft short (over current conditions just under the current limit), adds 0.5 mA to the IPWR current.
PARALLELING OF OUTPUTS
Using MOSFETs as output switches permits connecting any combination of outputs together. RDS(ON) of MOSFETs have an inherent positive temperature coefficient providing balanced current sharing between outputs without destructive operation (bipolar outputs could not be paralleled in this fashion as thermal run-away would likely occur). The device can even be operated with all outputs tied together. This mode of operation may be desirable in the event the application requires lower power dissipation, or the added capability of switching higher currents. Performance of parallel operation results in a corresponding decrease in RDS(ON) while the Output OFF Open Load Detect Currents and the Output Current Limits increase correspondingly (by a factor of eight if all outputs are paralleled). Less than 125 m RDS(ON) at 25C with current
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FUNCTIONAL DESCRIPTION INTRODUCTION
limiting of eight to 24 A will result if all outputs are paralleled together. There will be no change in the over voltage detect or the OFF output threshold voltage range. The advantage of paralleling outputs within the same 33298 affords the existence of minimal RDS(ON) and output clamp voltage variation between outputs. Typically, the variation of RDS(ON) between outputs of the same device is less than 0.5 percent. The variation in clamp
voltages, potentially affecting dynamic current sharing, is less than five percent. Paralleling outputs from two or more different devices is possible, but it is not recommended. There is no guarantee the RDS(ON) and clamp voltage of the two devices will match. System level thermal design analysis and verification should be conducted whenever paralleling outputs; particularly where different devices are involved.
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CS
SCLK
Analog Integrated Circuit Device Data Freescale Semiconductor
D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 OD* OD* OD* OD* OD* OD* D0* D1* D2* D3* D4* D5* D6* D7* Old Data New Data DO7 Old Data New Data DO0 Data Transfer Timing (General) CS High-to-Low CS Low-to-High SO SI SO pin is enabled. Output Status information transferred to Output Shift Register. Data from the Shift Register is transferred to the Output Power Switches. Will change state on the rising edge of the SCLK pin signal. Will accept data on the falling edge of the SCLK pin signal.
SI
D0
D1
SO
OD*
OD*
Output 7
Figure 18. Data Transfer Timing
Output 0
NOTES: 1.Reset pin is in a logic high-state during the above operation. 2.D0, D1, D2, ..., and D15 relate to the ordered entry of program data into the MC33298 with D0/D8 bits (MSB) corresponding to Output 7 and D7/D15 corresponding to Output 0. 3.D0*, D1*, D2*, ..., and D7* relate to the ordered data out of the 33298 with D0* bit (MSB) corresponding to Output 7. 4.OD* corresponds to Old Databits. 5.For brevity, only DO7 and DO0 are shown which respectively correspond to Output 7 and Output 0.
FUNCTIONAL DESCRIPTION INTRODUCTION
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FUNCTIONAL DESCRIPTION FAULT LOGIC OPERATION
FAULT LOGIC OPERATION INTRODUCTION
The MCU can perform a parity check of the fault logic operation by comparing the command 8-bit word to the status 8-bit word. Assume after system reset, the MCU first sends an 8-bit command word to the 33298. This word is called Command Word 1. Each output to be turned ON will have its corresponding data bit low. Refer to the data transfer timing illustration in Figure 16. As Command Word 1 is being written into the Shift register of the 33298, a status word is being simultaneously written and received by the MCU. However, the word being received by the MCU is the status of the previous write word to the 33298, Status Word 0. If the command word of the MCU is written a second time (Command Word 2 = Command Word 1), the word received by the MCU, Status Word 2, is the status of Command Word 1. The timing diagram illustrated in Figure 16 depicts this operation. Status Word 2 is then compared with Command Word 1. The MCU will Exclusive OR Status Word 2 with Command Word 1 to determine if the two words are identical. If the two words are identical, faults do not exist. The timing between the two write words must be greater than 100 s to receive proper drain status. The system data bus integrity may be tested by writing two like words to the 33298 within a few microseconds of each other. each output separately such that the outputs are independent in operation. A VPWR Over Voltage Detect is a global nature causing all outputs to be turned OFF.
OVER TEMPERATURE FAULT
Patent pending Over Temperature Detect and shutdown circuits are specifically incorporated for each individual output. The shutdown following an Over Temperature condition is independent of the system clock and other logic signal. Each independent output shuts down at 155C to 185C. When an output shuts down due to an Over Temperature Fault, no other outputs are affected. The MCU recognizes the fault since the output was commanded to be ON and the status word indicates it is OFF. A maximum hysteresis of 20C ensures an adequate time delay between output turn OFF and recovery. This avoids a very rapid turn ON and turn OFF of the device around the Over Temperature threshold. When the temperature falls below the recovery level for the Over Temperature Fault, the device will turn on only if the Command Word during the next write cycle indicates the output should be turned ON.
OVER VOLTAGE FAULT
An Over Voltage condition on the VPWR pin causes the 33298 to shut down all outputs until the over voltage condition is removed and the device is re-programmed by the SPI. The over voltage threshold on the VPWR pin is specified as 28 V to 36 V with 1.0 V typical hysteresis. Following the over voltage condition, the next write cycle sends the SO pin the hexadecimal word $FF (all ones) indicating all outputs are turned off. In this way, potentially dangerous timing problems are avoided and the MCU reset routine ensures an orderly startup of the loads. The 33298 does not detect an over voltage on the VDD pin. Other external circuitry, such as a universal voltage monitor, is necessary to accomplish this function.
INITIAL SYSTEM SETUP TIMING
The MCU can monitor two kinds of faults: 1. Communication errors on the data bus 2. Actual faults of the output loads After initial system start up or reset, the MCU will write one word to the 33298. If the word is repeated within approximately five microseconds of the first word, the word received by the MCU, at the end of the repeated word, serves as a confirmation of data bus integrity (1). At start up, the 33298 will take 25 to 100 s before a repeat of the first word should be repeated at least 100 s later to verify the status of the outputs. The SO of the 33298 will indicate any one of four faults. The four possible faults are: 1. Over Temperature 2. Output OFF Open Fault 3. Short Fault (over current) 4. VPWR Over Voltage Fault. All of these faults, with the exception of the Over Voltage Fault, are output specific. Over Temperature Detect, Output OFF Open Detect, and Output Short Detect are dedicated to
OUTPUT OFF OPEN LOAD FAULT
An Output OFF Open Load Fault is the detection and reporting of an open load when the corresponding output is disabled (input in a logic high state). To understand the operation of the Open Load Fault detect circuit; see Figure 17. The Output OFF Open Load Fault is detected by comparing the drain voltage of the specific MOSFET output to an internally generated reference. Each output has one dedicated comparator for this purpose.
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FUNCTIONAL DESCRIPTION FAULT LOGIC OPERATION
33298
Low = Fault RL
VPWR
faulted threshold. The circuit automatically returns to normal operation once the condition causing the Open Load Fault is removed.
SHORTED LOAD FAULT
MOSFET OFF
+ -
50 A
Output
A short load, or over current fault can be caused by any output being shorted directly to supply, or an output experiencing a current greater than the current limit. There are three safety circuits progressively in operation during load short conditions providing system protection. They are: 1. The output current of the device is monitored in an analog fashion using a SENSEFETTM approach and current limited. 2. The output current of the device is sensed by monitoring the MOSFET drain voltage. 3. The output thermal limit of the device is sensed, and when attained, causes only the specific faulted output to be latched OFF, allowing all remaining outputs to operate normally. Each of the three protection mechanisms are incorporated in their output providing robust independent output operation. The analog current limit circuit is always active, monitoring the output drain current. An over current condition causes the gate control circuitry to reduce the gate-to-source voltage imposed on the output MOSFET, re-establishing the load current in compliance with current limit (1.0 to 3.0 A) range. Time required for the current limit circuitry to act is less than 20 s. Therefore, currents higher than 1.0 to 3.0 A will never be seen for more than 20 s (a typical duration is 10 s). If the current of an output attempts to exceed the predetermined limit of 1.0 to 3.0 A (2.0 A nominal), the VDS voltage will exceed the VThres voltage and the over current comparator will be tripped, illustrated in Figure 18.
VThres 2.5 to 3.5 V
Figure 19. Output OFF Open Load Fault An Output OFF Open Load Fault is indicates when the output voltage is less than the Output Threshold Voltage (VThres) of 0.6 to 0.8 x VDD. Since the 33298 outputs function as switches, during normal operation, each MOSFET output should either be completely turned ON or OFF. By design, the threshold voltage was selected to be between the ON and OFF voltage of the MOSFET. During normal operation, the ON state VDS voltage of the MOSFET is less than the threshold voltage and the OFF state VDS voltage is greater than the threshold voltage. This design approach provides using the same threshold comparator for Output Open Load Detect in the OFF state and Short Circuit Detect in the ON state. See Figure 18 for an understanding of the Short Circuit Detect circuit. With VDD = 5.0 V, an OFF state output voltage of less than 3.0 V will be detected as an Output OFF Open Load Fault while voltages greater than 4.0 V will not be detected as a fault. The 33298 has an internal pull-down current source of 50 A, illustrated in Figure 17 between the MOSFET drain and ground. This current source prevents the output from floating up to VPWR if there is an open load or internal wire bond failure. The internal comparator compares the drain voltage with a reference voltage, VThres (0.6 to 0.8 x VDD). If the output voltage is less than this reference voltage, the 33298 will declare the condition to be an open load fault. During steady-state operation, the minimum load resistance (RL) required to prevent false fault reporting during normal operation can be located using the following equation: Therefore, the load resistance necessary to prevent false open load fault reporting is (using Ohm's Law) equal to 92 k or less. During output switching, especially with capacitive loads, a false output OFF Open Load Fault may be triggered. To prevent this false fault from being reported an internal fault filter in the range of 25 to 100 s is incorporated. The duration in which a false fault may be reported is a function of the load impedance (RL,CL,LL), RDS(on), and COUT of the MOSFET as well as the supply voltage (VPWR). The rising edge of CS triggers a built-in fault delay timer which must time-out (25 or 100 s) before the fault comparator is enabled to detect at
33298
High = Fault
VPWR RL Output
MOSFET ON Digital
+ -
Analog +
-
Vref
VThres 2.5 to 3.5 V
Figure 20. Short Circuit Detect and Analog Current Limiting Circuit The status of SFPD determines whether the 33298 will shut down immediately, or continue to operate in an analog
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FUNCTIONAL DESCRIPTION FAULT LOGIC OPERATION
current limited mode until either the short circuit (over current) condition is removed or thermal shutdown is reached. Grounding the SFPD pin enables the short fault protection shutdown circuitry. Consider a load short (output short to supply) occurring on an output before, during, and after output turn ON. When the CS signal rises to the high logic state, the corresponding output is turned ON, activating a delay timer. The duration of the delay timer is 70 to 250 s. If the short circuit takes place before the output is turned ON, the delay experienced is the entire 70 s to 250 s followed by shutdown. If the short occurs during the delay time, the shutdown still occurs after the delay time has elapsed. However, if the short circuit occurs after the delay time, shutdown is immediate (within 20 s after sensing). The purpose of the delay timer is to prevent false faults from being reported when switching capacitive loads. If the SFPD pin is at 5.0 V, or VDD, an output will not be disabled when an over current is detected. The specific output will, within 5.0 to 10 s of encountering the short circuit, go into an analog current limited mode. This feature is especially useful when switching incandescent lamp loads, where high in-rush currents experienced during startup last for 10 to 20 milliseconds. Each output of the 33298 has its own over current shutdown circuitry. Over temperature, and the over voltage faults are not affected by the SFPD pin's state. Both load current sensing and output voltage sensing are incorporated for Short Fault detection with actual detection occurring slightly after the onset of current limit. The current limit circuitry incorporates a SENSEFETTM approach to measure the total drain current. This calls for the current through a small number of cells in the power MOSFET to be measured and the result multiplied by a constant, giving the total current. Wherein output shutdown circuitry measures the drain-to-source voltage, shutting down the output if its threshold (VThres) is exceeded. Short fault detection is accomplished by sensing the output voltage and comparing it to VThres. The lowest VThres requires a voltage of 2.5 V to be sensed. For an enabled output, with VDD = 5.0 0.5 V, an output voltage in excess of 3.5 V will be detected as a short, or over current condition, while voltages less than 2.5 V will not be detected as shorts.
SFPD PIN VOLTAGE SELECTION
Since the voltage condition of the SFPD pin controls the activation of the short fault protection (i.e., shutdown) mode equally for all eight outputs, the load having the longest duration of in-rush current determines what voltage (state) the SFPD pin should be. Usually if at least one load is, an incandescent lamp for example, the in-rush current on that input will be milliseconds in duration. Therefore, setting SFPD at 5.0 V will prevent shutdown of the output due to the in-rush current. The system relies only on the over temperature shutdown to protect the outputs and the loads. The 33298 was designed to switch GE194 incandescent lamps, or equivalents, with the SFPD pin in a grounded state. Considerably larger lamps can be switched with the SFPD pin held in a high logic state. Sometimes both a delay period greater than 70 to 250 s (current limiting of the output) followed by an immediate over current shutdown is necessary. This can be accomplished by programming the SFPD pin to 5.0 V for the extended delay period, allowing the outputs to remain ON in a current limited mode, then grounding it to accomplish the immediate shutdown after a period of time. Additional external circuitry is required to implement this type of function. An MCU parallel output port can be devoted to controlling the SFPD voltage during and after the delay period, is often a much better method. In either case, care should be taken to execute the SFPD start-up routine every time start-up or reset occurs.
UNDER VOLTAGE SHUTDOWN
An under voltage VDD condition will result in the global shutdown of all outputs. The under voltage threshold is between 2.5 V and 3.5 V. When VDD goes below the threshold, all outputs are turned OFF, thereby resetting the Serial Output Data register to indicate the same. An under voltage condition at the VPWR pin will not cause output shutdown and reset. When VPWR is between 5.5 V and 9.0 V, the outputs will operate per the command word. However, the status as reported by the SO pin may not be accurate below 9.0 V VPWR. Proper operation at VPWR voltages below 5.5 V are not be guaranteed.
DECIPHERING FAULT TYPE OVER CURRENT RECOVERY
If the SFPD pin is in a high logic state, the circuit returns to normal operation automatically after the short circuit is removed (unless thermal shutdown has occurred). If the SFPD pin is grounded and over current shutdown occurs, removing the short circuit will result in the output remaining OFF until the next write cycle. If the short circuit is not removed, the output will turn ON for the delay time (70 to 250 s) and then turn OFF for every write cycle commanding a turn ON. The 33298 SO pin can be used to determine what kind of system fault has occurred. With eight outputs having open load, over current, over temperature, and over voltage faults; a total of 25 different faults are possible. The SO status word received by the MCU will be compared with the word sent to the 33298 during the previous write cycle. For a specific output, if the SO bit compares with the corresponding SI bit of the previous word; the output is operating normal with no fault. Only when the SO bit and previous word SI bit differ is there a fault indicated. If the two words are not the same, the MCU should be programmed to determine which output or outputs are faulted. If, for a specific output, the initial SI command bit were logic high, the output would be programmed to be OFF; if,
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FUNCTIONAL DESCRIPTION FAULT LOGIC OPERATION
upon the next command word being entered, a logic low came back on SO, for that specific output's corresponding bit, an Output-OFF Open-Load fault would be indicated. The resulting SO bit, for that specific output, would be different from that entered during the previous word for that SI bit, indicating the fault. The eight output-off open-load faults are therefore most easily detected. If for a specific output, the initial SI command bit were a logic low, calling for the output to be programmed on; upon the next word command being entered, the corresponding bit came back with a logic high on SO, an output over current fault would be indicated. An over current fault is always reported by the SO output and is independent of the logic state existing on the SFPD pin. When the SFPD pin is in a logic high state, an over current condition will be reported on the SO pin. However, limiting output current is in effect and the output is permitted to operate if the over current condition does not drive output into an over temperature fault. An over temperature fault will shutdown the specific output effected for the duration of the over temperature condition. Over current and over temperature faults are often related. Turning the effected output switches OFF and waiting for some time to allow the output to cool down should make these types of faults go away. Soft over current faults can sometimes be determined over hard short faults and over temperature faults by observing the time required for the device to recover. However, in general over current and over temperature faults can not be differentiated in normal application usage. An advantage of the synchronous serial output is multiple faults can be detected with only one (SO) pin being used for fault status reporting. If VPWR experiences an over voltage condition, all outputs will immediately be turned OFF and remain latched off. A new
command word is required to turn the outputs back on following an over voltage condition.
OUTPUT VOLTAGE CLAMPING
Each output of the 33298 incorporates an internal voltage clamp to provide fast turn-off and transient protection of the output. Each clamp independently limits the drain to source voltage to 53 V at drain currents of 0.5 A and keeps the output transistors from avalanching by causing the transient energy to be dissipated in the linear mode. See Figure 19. The total energy clamped (EJ) can be calculated by multiplying the current area under the current curve (IA) times the clamp voltage (VCL) times the duration the clamp is active (t). Characterization of the output clamps, using a single pulse non-repetitive method at 0.5 A, indicate the maximum energy to be 50 mJ at 150C junction temperature per output.
Drain-to-Source Clamp Voltage (VCL = 65 V)
Drain Voltage
Drain Current (ID = 0.5A)
Clamp Energy (EJ = IA x VCL x t)
VPWR
Drain-to-Source ON Voltage (VDS(on)) GND
Current Area (IA)
Time
Figure 21. Output Voltage Clamping
THERMAL CHARACTERIZATION THERMAL MODEL
Logic functions take up a very small area of the die and generate negligible power. In contrast, the output transistors take up most of the die area and are the primary contributors of power generation. The thermal model illustrated in Figure 20 was developed for the 33298 mounted on a typical PC board. The model is accurate for both steady state and transient thermal conditions. The components RD0 through RD7 represent the steady state thermal resistance of the silicon die for transistor outputs 0 through 7, while CD0 through CD7 represent the corresponding thermal capacitance of the silicone die translator outputs and plastic. The device area and die thickness determine the values of these specific components. The thermal impedance of the package from the internal mounting flag to the outside environment is represented by the terms Rpkg and Cpkg. The steady state thermal resistance of leads and the PC board make up the steady state package thermal resistance, Rpkg. The thermal capacitance of the package is made up of the combined capacitance of the flag and the PC board. The mode compound was not modeled as a specific component but it is factored into the other overall component values. The battery voltage in the thermal model represents the ambient temperature the device and PC board are subjected to.The IPWR current source represents the total power dissipation and is calculated by totalling the power dissipation of each individual output transistor. This is easily accomplished by knowing RDS(on) and load current of the individual outputs. Very satisfactory steady state and transient results are experienced with this thermal model. Tests indicate the model accuracy to have less than 10 percent error. Output interaction with an adjacent output is believed to be the main contributor to the thermal inaccuracy. Tests indicate little or no detectable thermal affects caused by distant output transistors isolated by one or more other outputs. Tests were conducted with the device mounted on a typical PC board placed horizontally in a 33 cubic inch still air enclosure. The PC board was made of FR4 material measuring 2.5 by 2.5
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FUNCTIONAL DESCRIPTION FAULT LOGIC OPERATION
inches, having double sided circuit traces of 1.0 ounce copper soldered to each device pin. The board temperature was measured with thermal couple soldered to the board surface one inch away from the center of the device. The ambient temperature of the enclosure was measured with a second thermal couple located over the center of one inch distance from device.
THERMAL PERFORMANCE
Figure 20 illustrates the worst case thermal component parameters values for the 33298 in the 20-pin plastic power DIP and the SOP-24 wide body surface mount package. pins 5, 6, 15, and 16 of the power DIP package are connected directly to the lead frame flag. The parameter values indicated take into account adjacent output combinations. The characterization was conducted over power dissipation levels of 0.7 to 17 W. The junction-to-ambient temperature thermal resistance was found to be 37C/W with a single output active (31C/W with all outputs dissipating equal power) and in conjunction with this, the thermal resistance from junction to PC board (Rjunction-board) was found to be 27C/W (board temperature, measure one inch from device center). Additionally, the thermal resistance from junction-toheatsink lead was found to approximate 10C/W. Devoting
additional PC board metal around the heatsinking pins improved Rpkg from 30 to 28 C/W. The SOP-24 package has pins 5, 6, 7, 8, 17, 18, 19, and 20 of the package connected directly to the lead frame flag. Characterization was conducted in the same manner as with the DIP package. The junction-to-ambient temperature resistance was found to be 40C/W with a single output active (34C/W with all outputs dissipating equal power0 and the thermal resistance from junction-to-PC board (Rjunction-board) to be 30C/W (board temperature, measure one inch from device center). The junction-to-heatsink lead resistance was found again to approximate 10C/W. Devoting additional PC board metal around the heatsinking pins for this package improved the Rpkg from 33 to 31C/W. The total power dissipation available is dependent on the number of outputs enabled at any one time. At 25C the RDS(on) in 450 m with a coefficient of 6500 ppm/C. For the junction temperature to remain below 150C, the maximum available power dissipation must decrease as the ambient temperature increases. Figures 21 and 22 depict the per output limit of current at ambient temperatures necessary when one, four, or eight outputs are enable ON. Figure 23 illustrates how the RDS(on) output value is affected by junction temperature.
Junction Temperature Node VD - TD (C) (Volts represent Die Surface Temperature) Output 0 Output 1 Output 2 Output 6 Output 7
Rd0
Cd0
Rd1
Cd1
Rd2
Cd2
Rd6
Cd6
Rd7
Cd7
IPWR (Steady State or Transient) (1.0 A = 1.0 W of Device Power Dissipation) Rpkg = Rleads +RPC Board
Flag Temperature Node
Cpkg = Cflag + CPC Board
Package
Rdx
()*
7.0 7.0
Cdx (F)*
0.002 0.002
Rpkg ()*
30 33
Cpkg (F)*
0.2 0.15
Ambient Temperature Node VA = TA (C) (1.0 V = 1C Ambient Temperature)
20 pin Dip SOP-24L
* = C/W, F = W s/C, IPWR = W, and VA = C
Figure 22. Thermal Model (Electrical Equivalent)
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION FAULT LOGIC OPERATION
IL(MAX),Maximum Current Per Output (A)
RDS(ON), Output ON Resistance ( )
3.0
1 Output ON (37C/W)
1.6 1.5 1.4 1.3 1.2 1.1 1.0
2.5 2.0 1.5 1.0 0.5 0 -50 -25 0 25
8 Outputs ON (31C/W) 4 Outputs ON (32C/W)
RDS(on)@150C=0.8 TJ =150C
VPWR = 13 V VDD = 5.0 V IOUT = 0.5 A
50
75
100 125 150
0.9 -50 -25
0
25
50
75
100 125 150
TA, Ambient Temperature (C)
TJ Junction Temperature (C)
Figure 23. Maximum DIP Package Steady State Output Current vs. Ambient Temperature
Figure 25. Maximum Output ON Resistance vs. Junction Temperature
IL(MAX),Maximum Current Per Output (A)
2.5 2.0 1.5 1.0 0.5
1 Output ON (40C/W)
RDS(on)@150C=0.8 TJ =150C
4 Outputs ON (35C/W)
8 Outputs ON (34C/W)
0 -50 -25
0
25
50
75
100 125 150
TA Ambient Temperature (C)
Figure 24. Maximum SOP Package Steady State Output Current vs. Ambient Temperature
33298
Analog Integrated Circuit Device Data Freescale Semiconductor
25
PACKAGE DIMENSIONS PACKAGE DIMENSIONS
PACKAGE DIMENSIONS
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the "98A" listed below.
DW SUFFIX EG SUFFIX (PB-FREE) 20-PIN PLASTIC PACKAGE 98ASB42344B ISSUE F
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Analog Integrated Circuit Device Data Freescale Semiconductor
REVISION HISTORY
REVISION HISTORY
REVISION 4.0
DATE 8/2006
DESCRIPTION OF CHANGES
* * * * *
5.0
10/2006
Implemented Revision History page Converted to Freescale format Update to the prevailing form and style Added EG suffix device Removed MC33298EG/R2 and replaced with MCZ33298EG in the Ordering Information block * Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from Maximum ratings on page 5. Added note with instructions to obtain this information from www.freescale.com.
33298
Analog Integrated Circuit Device Data Freescale Semiconductor
27
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MC33298 Rev. 5.0 10/2006

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